Glitching out-of-order processors?

[ezhes]

Lazy research q, but google isn't giving much here since it seems like the bulk of public work here focuses on simpler, slower uarchs. Does anyone have any favorite notes or resources on glitching OoO cores? Having considerable pain trying to get a reliable trigger landing since the pipeline state (especially for deep ROBs) is practically random due to the avalanche effect of all the other activity on the SoC and so trying to hit even a particular point in a program is turning out to be a nightmare. Are there any tricks here?